Tunnel field effect transistors (TFETs), which use a band-to-band tunneling (BTBT) mechanism, have been investigated as one of the most promising next-generation devices for low-power applications. However, scaling-down complementary metal oxide semiconductor (CMOS) transistors results in increased power consumption and short channel effects.
In conventional planar TFETs, the on current (Ion) is limited by the inversion layer thickness (tunneling area), which is only a couple of nanometers or less. See, for example, S. Cristoloveanu et al., “A Review of Sharp-Switching Devices for Ultra-Low Power Applications,” Journal of the Electron Devices Society, Vol. 4, no. 5, pgs. 215-226 (September 2016) (hereinafter “Cristoloveanu”). For instance, as shown in FIG. 2a of Cristoloveanu, with a planar TFET design the tunneling area is limited to a top corner portion of the source and drain. This tunneling area is small because the channel is only a couple of nanometers or less beneath the gate.
Therefore, TFET designs with increased tunneling area and Ion would be desirable.